The following patents are illustrative of the LSSD testing arrangements and organizations and should be referred to for detailed descriptions of their underlying principles. It should be understood that the present invention does not claim any novelty in the use of any particular LSSD architecture, but only in the broad architectural organization of a Diagnostic/Debugging system having an appropriate interface for accessing all of the latch contained state information resident in the LSSD registers of the Host computer.
U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System", application Ser. No. 297,543, filed Oct. 16, 1972, granted Jan. 1, 1974 to E. B. Eichelberger and of common assignee.
U.S. Pat. No. 3,761,695 entitled "Method of Level Sensitive Testing a Functional Logic System", application Ser. No. 298,087, filed Oct. 16, 1972, granted Sept. 25, 1973 to E. B. Eichelberger and of common assignee.
U.S. Pat. No. 3,784,907 entitled "Method of Propagation Delay Testing a Functional Logic System", application Ser. No. 298,071, filed Oct. 16, 1972, granted Jan. 8, 1974 to E. B. Eichelberger and of common assignee.
The following patents are cited as being generally exemplary of the system diagnostic art, particularly U.S. Pat. No. 3,786,430 entitled "Data Processing System Including a Small Auxiliary Processor for Overcoming the Effects of Faulty Hardware", application Ser. No. 198,881, filed Nov. 15, 1971, granted Jan. 15, 1974 to Johann Hajdu et al and of common assignee. This patent discloses an electronic data processing system comprising a main processor and an auxiliary processor and is designed to minimize the effects of hardware failure by intercepting the function of the main processor in the case of a hardware error. Although the auxiliary processor is in some sense a monitor, it is better described as an error processing system. It is linked to the data registers and function decoders of the main processor are designed solely so that it can accept the necessary input data in order to stimulate the operation of the main processor in the case of hardware failure. It then transfers the output data to the main processor once the simulated function is complete.
U.S. Pat. No. 3,585,599 entitled "Universal System Service Adapter", application Ser. No. 743,567, filed July 9, 1968, granted June 15, 1971 to D. C. Hitt and of common assignee. This patent discloses a universal adaptor which serves as an interface between its host computer and external equipment, another processor, for purposes of monitoring and testing the host. The adaptor is designed to receive diagnostic test control information from the external source for transmittal to the host system and to transmit system status information from the host to the external source. Testing is, however, limited to only certain hardware function, with test responses being of a pass/fail nature only. The transmitted information, i.e., from host to external equipment, is similarily limited to system status log messages.
U.S. Pat. No. 3,825,901 entitled "Integrated Diagnostic Tool", application Ser. No. 305,021, filed Nov. 9, 1972, granted July 23, 1974 to B. R. Golnek, Sr. et al and of common assignee. This patent discloses an integrated diagnostic tool which is an enhancement of the adaptor described in the Hitt patent, which permits testing and monitoring while the system is running at normal speed.
None of the above diagnostic system patents disclose a combination Diagnostic/Debugging processing system and are particularly absent of any suggestion of such a diagnostic tool specifically adapted and tailored to use with the LSSD design concept.